Abstract
In the context of the high-luminosity large hadron collider (HL-LHC) upgrade, this work presents the latest update on the design of the FPGA firmware responsible of particle track reconstruction in the pattern recognition mezzanine (PRM) of the hardware-based tracking for the trigger (HTT) system, a subsystem of the ATLAS experiment trigger and data acquisition system. This computationally demanding task relies heavily on two FPGA features: the embedded in silicon digital signal processing (DSP) components and the performance of an available high bandwidth memory (HBM). The document reports the mathematical algorithm used for track reconstruction and analyses a preliminary performance test. These considerations are then used to provide estimates on the DSP and HBM resource usage in order to prove the feasibility of the firmware design. Finally, key factors for a parallel design are identified and outlook presented.
Highlights
T HE expected increase in peak luminosity of the highluminosity large hadron collider to 7.5 × 1034 cm−2s−1 is driving the ATLAS experiment upgrade strategy for the trigger and data acquisition system [1] towards the implementation of precise hardware-based track reconstruction
The pattern recognition mezzanine (PRM) is a critical component of this system which mounts the FPGA assigned with the challenging computational task of performing a linear track fit and reconstruction
To achieve the best possible performance these two entities rely heavily on embedded digital signal processing (DSP) blocks and high bandwidth memory (HBM) [3], both of which can be found in the FPGA model under consideration in this document: the Altera Intel Stratix 10 MX 2100
Summary
T HE expected increase in peak luminosity of the highluminosity large hadron collider to 7.5 × 1034 cm−2s−1 is driving the ATLAS experiment upgrade strategy for the trigger and data acquisition system [1] towards the implementation of precise hardware-based track reconstruction. The hardware-based tracking for the trigger (HTT) system uses a combination of custom ASICs for pattern recognition and FPGAs to provide the software-based trigger system with access to tracking information, allowing for reduced pT trigger thresholds for primary lepton selections, while contributing to pile-up mitigation, essential for hadronic signatures. The pattern recognition mezzanine (PRM) is a critical component of this system which mounts the FPGA assigned with the challenging computational task of performing a linear track fit and reconstruction. In the PRM FPGA firmware architecture (Fig. 1) there are two modules which take care of the aforementioned task: the track fitter block (TFB) and the parameter calculator (PC). Student at the Departement de physique nucleaire et corpusculaire, University of Geneva, Switzerland
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