Abstract
Advanced Process Control (APC) has been widely applied in state-of-the-art semiconductor industries for the everlasting pursuit of cycle time reduction, higher yield, and zero scraps. Inline metrology is thus valuable input for the improvement of wafer-to-wafer and within-wafer CD variations originated from either abnormality or noise of different processes. Implementing a suitable APC scheme to process flow remains a challenging task for engineers. In most cases, it is enough to implement the APC to only one single pattern on Chip. However, for multi-purpose chip design, the CD control of multiple patterns is becoming important. In this paper, we presented an APC workflow to control the CD of two different patterns. It is shown that, with the same amount of APC process layers, we were able to improve from single pattern CD control to dual pattern CD control. The final process variations of two patterns can be controlled within ±0.5 nm.
Published Version
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