Digital Phase Locked Loops

Abstract

The paper describes the phase locked loop (PLL) in detail. Emphasis is on Digital Phase Locked loops (DPLL) and All-Digital Phase Locked Loops (ADPLL). Important parameters of the PLLs are described. Different sub-blocks of DPLL and ADPLL are described and discussed in detail. An example design of ADPLL is also discussed. Digital and All Digital PLLs are gaining popularity because of their ease of implementation in FPGA’s and ASIC’s.