A digitally controlled phase-locked loop with fast locking scheme for clock synthesis application

Abstract

For clock generation and clock recovery, charge pump phase-locked loops (CPPLLs) are widely employed inside ICs since they can be integrated on a standard CMOS process and have the ability to remove DC phase offset with just a passive loop filter. However, owing to complex loop characteristic and precision required for analog blocks, the design is not simple. All digital phase-locked loop (ADPLL) achieved 50-cycle acquisition time by sweeping the whole tuning range through a modified binary search. Due to a fixed sweeping algorithm, acquisition time is independent of VCO free-running frequency. Also, adaptive gear-shifting phase-locked loop (AGPLL) brings acquisition time within 40 cycles by adjusting the loop bandwidth proportional to the input phase differences. In spite of poor jitter performance, digital implementations have started to draw more attention since they yield better testability, programmability, stability, and transplantation over various processes. In this work the authors present a digitally controlled phase-locked loop (DCPLL) which reduces acquisition time by utilizing a digital frequency-difference detector (DFDD). Whereas the arbiter of the ADPLL generates only binary results of 'fast' or 'slow', the DFDD supports the functions of measuring frequency difference and an arbiter. Thereby, the DCPLL acquisition time is reduced compared to that of the ADPLL, while its locking performance remains independent of free-running frequency. A prototype DCPLL has been implemented in a 0.6 /spl mu/m triple metal CMOS process.