Digital phase-locked loop with jitter bounded

Abstract

A design of an all-digital phase-locked loop (DPLL) with direct frequency synthesis is proposed for generating signals that satisfy preimposed requirements on jitter over any given range of frequencies. Control of the jitter is obtained by means of a frequency-phase window comparator which compares the bit overflow/underflow of the direct synthesis (accumulator-type) digital controlled oscillator output to a fixed frequency-phase window, and thus ensures that the jitter of the generated signal is bounded within the preassigned limits. Acquisition of frequency and phase lock are achieved through successive approximation, which reduces the acquisition time of the DPLL. The concept has been confirmed through laboratory experiments to synthesize frequencies from 10 Hz to 1.544 MHz with a 6.25% upper bound on the jitter.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>