Capacitor free phase locked loop design in 45nm

Abstract

The paper describes the design of a capacitor-free phased locked loop realized using 45 nm technology. Phase locked loops (PLL) find widespread application in electronic circuits, especially in generating high speed clocks for digital chips. Traditional analog PLL designs use capacitors and resistors in the charge pump and the filter circuits. These components occupy large area, adding to the circuit cost; in addition to consuming more power. These limitations can be removed by building a completely digital PLL. But fully digital PLLs have their own drawbacks, especially inaccuracies due to the quantization errors, coarser-grain control of the output frequency generation and errors at higher frequencies. As a result, completely digital PLLs are not suited for generating high frequency signals. In this paper, we present the design of a capacitor-free PLL. It retains the analog Voltage Controlled Oscillator (VCO) in order to run accurately at high frequencies, but replaces all other analog components with their digital counterparts. Incorporation of the digital components eliminates the capacitors and resistors in the circuit and reduces the circuit area and power consumption, while also making the design independent of thermal noise, aging, mismatch and leakage due to the charge pump.