Digital Fractional-<inline-formula> <tex-math notation="LaTeX">$N$ </tex-math> </inline-formula> PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System

Abstract

Frequency-modulated continuous-wave (FMCW) radar requires low in-band phase noise, fast-settling high-frequency phase-locked loops (PLLs). We propose a new third-order continuous-time time-to-digital converter (TDC) that shapes quantization noise so that the TDC quantization noise no longer determines the in-band phase noise of a digital PLL. The new TDC allows a digital PLL to have an in-band phase noise performance similar to that of an analog PLL. Prototype 30- and 40-GHz PLLs, fabricated in 65-nm CMOS as sources for a 240-GHz scanning FMCW radar, consume 34.8 and 40 mW, respectively. The 30-GHz prototype PLL has a normalized phase noise of −213 dBc/Hz2 (at 100-kHz offset) and an FoMJitter of −230 dB (from 10 kHz to 1 MHz), thanks to the measured 182 fs integrated rms noise of TDC.