Abstract

This work presents a digital calibration technique in continuous-time (CT) ΔΣ analog to digital (A/D) converters. The converter is clocked at 144MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching (DEM) is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65nm CMOS process. The maximum simulated signal-to-noise and distortion ratio (SNDR) is 67.1dB within 9MHz bandwidth.

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