Abstract
This work presents a digital calibration technique in continuous-time (CT) delta-sigma ($$\Delta \Sigma$$ΔΣ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT $$\Delta \Sigma$$ΔΣ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.
Highlights
Delta-Sigma ADCs have increased in popularity in recent years
The feedback signal propagate through DAC3 and the proportional path (PI path) to act as a direct feedback around the quantizer
After it is inserted through a selected unit element, it appears at the output of the DR modulator
Summary
Delta-Sigma ADCs have increased in popularity in recent years These converters typically use higher order structures with multi-bit quantizers. The linearity of the outermost DAC lies in the feedback loop impairs the SNDR the most. Mismatches in this DAC is directly fed into the system in parallel with the input signal. A digital calibration circuit is implemented to compensate for mismatches in the outermost DAC. These mismatches are estimated using digital cross-correlation between the digital output and an externally injected pseudo random test signal.
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