Digital background calibration for pipelined ADC and implementation of Full FPGA verification platform

Abstract

The convergence speed is an important indicator of the digital background calibration technique for pipelined ADC. A Split-ADC architecture is used to calibrate the error resulting from capacitor mismatches and finite opamp dc gain in this work. Two channel ADCs, one with equivalent 1% interstage gain error in the first stage and the other with 2%, compose the “split ADCs” which are implemented on a FPGA chip. Simulation results show the interstage gain will converge in approximately 105 conversions and the interstage gain curve become smoother. With calibration, SFDR enhances from 79.4dB dB to 93.7dB and SNDR enhances from 58.9dB to 81.6dB.