Digital Architecture for Multi-Channel Histogram Computation in Real-Time

Abstract

In this contribution we present a real-time computation solution for multi-channel histograms at high-performance on Field-Programmable Gate Arrays (FPGAs). Being basic, yet highly useful instruments, histograms find applications in a wide variety of fields, playing a big role in compression and elaboration of large amount of data. Many solutions have already been developed by Academia and Industry, mostly relying on general-purpose Central Processing Units (CPUs) or full-custom Application-Specific Integrated Circuits (ASICs). Notwithstanding being mostly satisfying in terms of ease of use and flexibility (CPUs) on one side, or performance (ASICs) on the other, these solutions have shown to lack in balancing the tradeoff between these features. Another big point of interest is the often needed large storage capability for certain applications. To satisfy these requirements, we present a hybrid hardware and software innovative implementation of a real-time multi-channel histogram generator in an FPGA-based system, helped by a soft processor core implemented in the same FPGA fabric. In this way, the best performance of parallel and temporal computing merge into a firmware/software co-design. This solution features large availability of DDR memory, accessible through a Direct Memory Access (DMA), lower utilization of the precious FPGA resources with respect to the full-FPGA approach, real-time behavior and simplified, yet efficient, interface to the MicroBlaze, the soft core Reduced Instruction Set Computer (RISC), optimized for Xilinx FPGAs. IP-Cores and libraries allow the user-friendly Processing System to be connected to the programmable logic part to exploit its high performance in a flexible way. The system has been successfully tested on Xilinx 28-nm 7-Series devices connected to a 256 MB DDR3 memory, reaching performance in the order of 50 Msps and using a state–of–the–art, FPGA-based, multichannel, Time-to-Digital Converter (TDC) as event generator.