Asymmetric Core Computing for U.S. Army High-Performance Computing Applications

Abstract

Abstract : High-performance computing (HPC) is in a state of transition. HPC users have traditionally relied upon two things to supply them with processing power: speed of the central processing units (CPUs) and the scalability of the system. There are problems with this approach. Physical limitations are curtailing clock speed increases in general-purpose CPUs, the von Neumann load-execute-store approach does not map well to every computational problem, and systems of thousands of processors might be very inefficient depending upon processor interconnection limitations. Several versatile, commodity-based options are coming on line that could help address these deficiencies. Options now include throughput architectures such as graphics processing units (GPUs), reconfigurable systems built on field programmable gate arrays (FPGAs), multi- and many-core x86-based systems, and heterogeneous systems such as the Cell processor (incorporating a standard CPU and vector processing units). Each of these can be used to provide performance that, at one time, was only available by using Application Specific Integrated Circuits (ASICs) or large-scale fixed HPC assets. Newer methodologies hold out the hope of being more cost efficient and deployable along with providing faster deployment and development times and allowing the use of algorithms that remain modifiable at all stages of development and fielding. This report discusses our research on blending these asymmetric computing resources and addresses their use from the U.S. Army HPC perspective. We focus on the different methodologies and discuss performance from the perspective of kernels and applications that are relevant to fielding HPC technologies that will benefit the U.S. Army warfighter.