Base64 Encoding on OpenCL FPGA Platform

Abstract

Base64 encoding has many applications on the Web. Previous studies are focused on improving the efficiency of Base64 encoding on central processing units (CPUs). As field-programmable gate arrays (FPGAs) are becoming promising heterogeneous computing components in high-performance computing (HPC), and high-level synthesis (HLS) is more mature, we are motivated to optimize Base64 encoding on an FPGA using HLS. In this paper, we explain the algorithm, converts the algorithm to a kernel written in Open Computing Language (OpenCL), and optimize the kernel targeting an Intel Arria 10 FPGA. We evaluate the performance and power of the kernel implementations on the CPU, graphics processing units (GPUs), and FPGA computing platforms. The experimental results show that we can significantly improve the performance of Base64 encoding with the FPGA-specific optimizations. Compared to an Intel Xeon Platinum 8167 CPU, an Nvidia Tesla K80 GPU, and an Nvidia Tesla P100 GPU, the performance (the number of cycles per byte) of Base64 encoding on an Arria10-based FPGA platform is 3.98X higher than that on the K80 GPU, 17X higher than that on the CPU, and 1.83X lower than that on the P100 GPU for large input data sizes. The performance per watt on the FPGA is 1.1X lower than that on the P100 GPU, and 8.25X and 13.2X higher than that on the CPU and the K80 GPU, respectively.