Differential split-level CMOS logic for subnanosecond speeds

Abstract

Subnanosecond gate delays (0.8 ns) have been measured on complex logic gates (e.g. sum functions of a full adder) designed in the differential split-level CMOS circuit technique. This high speed has been achieved by reducing the logic swing (2.4 V) on interconnect lines between logic gates, by using current controlled cascoded cross-coupled NMOS-PMOS loads, by using combined open NMOS drains as outputs, and by using shorter channel lengths (L/SUB eff/=1 /spl mu/m) for the NMOS devices in the logic trees with reduced maximum drain-source voltages to avoid reliability problems. Extra ion implantation protects these transistors from punchthrough.