Dielectrophoretic Alignment of Functional Nanowires for Chemical Sensing Application

Abstract

Dielectrophoresis has received much attention owing to its capability to manipulate the polarizable nanowires at the specific locations on a substrate. Bottom-up integration of batch-synthesized nanowires with CMOS circuitry represents significant step toward the multifunctional miniaturized chip with the chemical diversity. We investigate the spatially-confined dielectrophoretic nanowires alignment on the parallel electrode array, covered by the dielectric layer, where they tend to repel each other because of the local electrostatic interaction of the polarized charges between them. Furthermore, the local capacitive coupling between the assembled nanowires and biased electrodes determines the final configuration of the nanowires relative to the electrodes. By using this combination of long- and short-range forces, it was observed that the uniformly-spaced nanowire array can be readily obtained over large area (~5×5 mm2) and even expandable to the entire wafer. Theoretical calculation and experimental data show that we can achieve the spacing-controlled nanowire array at the desired locations with the excellent end-to-end registration. Its combination with the periodic array of micron-scale recessed photoresist well produced the ultrahigh density nanowire device array, ~106 devices/cm2, on a substrate with sub-micron registration accuracy and high assembly yield exceeding ~90%. Post-assembly process including the electrodeposition provides a mechanically robust and low-resistant contact to the assembled nanowires while it also removes the misaligned nanowires. Device isolation using a dry etch completes the individual single nanowire device made of the metallic and semiconducting materials. They turned out to be all functional, achieving ~90% yield of single nanowire device fabrication on the desired sites, sparsely distributed within a chip. This scheme is also applicable to the integration of individual semiconducting nanowires with the desired locations on the complex circuitry which typically includes the metal interconnects, discrete devices, and topographical profiles.