Dielectric scaling of a zero-Schottky-barrier, 5nm gate, carbon nanotube transistor with source/drain underlaps

Abstract

The effect of gate dielectric on coaxially gated, Schottky-barrier, carbon nanotube field-effect transistors with source and drain underlaps is investigated. For 2nm thick dielectrics, the substitution of SiO2 with ZrO2 has little effect on the on-current and the subthreshold slope. The principal effect is a change in the intrinsic and parasitic gate capacitances which affects the delay time, cut-off frequency, and Coulomb blockade of the ambipolar leakage current. Using a relatively low-K gate dielectric (as opposed to a high-K gate dielectric) increases the speed performance by reducing parasitic components of the gate capacitance. For a 50nm long, 1.5nm diameter, zero-Schottky-barrier carbon nanotube (CNT) with a 5nm gate and a 2nm SiO2 dielectric, we obtain a delay time of 31fs, a cutoff frequency of 8.9THz, an inverse subthreshold slope S=66mV∕dec, and an on-off current ratio of 8×105 with VDD=0.4V. Oxide thickness dependence of the on-off current ratio, inverse subthreshold slope, and intrinsic cut-off frequency is also investigated.