Dielectric defects controlling instability in InGaAs n-MOSFETs with Al<inf>2</inf>O<inf>3</inf>/ZrO<inf>2</inf> gate stack

Abstract

Instability under positive bias stress (DC and AC) in InGaAs channel nMOSFETs with a a 1nmAl <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /5nmZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stack is studied. It is determined that the threshold voltage shift (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) during stress is primarily caused by a recoverable electron trapping at pre-existing defects, which are located pre-dominantly in the Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> interfacial layer (IL). Generation of new electron trapping defects is found to occur in the IL, in the region close to the substrate, while trap generation in the high-k dielectric is negligible. The ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> recovery impacts the degradation dependency on the stress duty cycle and frequency.