Abnormal Positive Bias Temperature Instability Induced by Dipole Doped N-Type MOSCAP

Fu-Yuan Jin,Yen-Cheng Chang,Kai-Chun Chang,Chien-Yu Lin,Fong-Min Ciou,Yu-Shan Lin,Yun-Hsuan Lin,Jih-Chien Liao,Wei-Chun Hung,Ting-Tzu Kuo,Ting-Chang Chang

doi:10.1109/jeds.2019.2932603

Abstract

This work performs fundamental electrical measurements and a positive bias temperature instability (PBTI) test on an N-type metal oxide semiconductor capacitor (MOSCAP) and a La2O3 dipole-doped N-type MOSCAP. Experimental results show that the dipole-doped N-type MOSCAP has a lower threshold voltage and gate current leakage than do the N-type MOSCAP. After positive bias stress, an abnormal gate current leakage decrease appears in both dipole-doped and normal N-type MOSCAPs under short term stress. Analysis of capacitance and gate current measurements indicate that electron trapping and defect generation cause the change in gate current after positive bias stress. Generally, devices with higher gate leakage have more severe degradation after PBTI. However, in this work, the dipole sample shows a lower initial gate current leakage but higher gate current degradation than those found in the control sample after PBTI. Based on the electrical measurement results and the energy band simulation, a conduction model was proposed to explain the abnormal PBTI of the dipole-doped N-type MOSCAP.

Highlights

In the development of metal oxide semiconductor field effect transistors (MOSFETs), scaling down the size is the main way to enhance performance
It is evident that the gate current of the dipole sample after threshold voltage correction is smaller than the control sample
Short term stress can be attributed to electron trapping in HfO2, shown in Fig. 4 (a) A rise in the energy band induced by trapping electrons in HfO2 makes it more difficult for electrons in the N-substrate to tunnel to the gate, which causes a decrease in gate current leakage

Summary

Introduction

In the development of metal oxide semiconductor field effect transistors (MOSFETs), scaling down the size is the main way to enhance performance. In the past production of MOSFETs, several ways were used to lower the threshold voltage, such as impurity doping adjustment, gate metal replacement, and oxide thickness reduction [1]–[4]. Fin Field-Effect Transistor (FinFET) is the novel structure for further minimize the MOSFET size. The most effective way to tune the threshold voltage of FinFET is gate multi metal layer. A mono dipole layer can achieve the same effect as using multi-metal in terms of threshold voltage adjustment because the dipole layer induces dipole in HfO2/ SiO2 interface and changes the threshold voltage of the FinFET. The HfO2 gate dielectric layer was doped with La or Y for the adjustment on the MOSFET threshold voltage [9]–[10]. The reliability of such a doped gate dielectric layer becomes worse after doping [11]–[12]

Methods

Results

Conclusion