Die level thinning after bonding on the substrate in 3D packaging

Abstract

This paper aims to realize heterogeneous integrated packaging technology for high integration by applying a thinning process technology for controlling the thickness of chipsets used in packaging, i.e., A technology for processing silicon dies with a thickness of 100 um or less and a technology for handling thinning ultrasmall dies. We combine wet etching with dry etching to fit an effective and practical experimental plan. Anisotropic etching in KOH solutions and ICP etching of silicon die bonding on a glass substrate are investigated. Die with copper wiring is fabricated and pasted on the substrate to achieve selective etching of the whole device. The topography of the die surface and corner is analyzed to prevent the influence on the second layer stacking process.