Abstract
The piezoresistive property of silicon nanowires (SiNWs) has been proven as one of the best candidates for strain sensors and now being explored in silicon transistors to improve the performance. In this article, we have numerically simulated and fabricated the junctionless nanowire (NW) field-effect transistor (JL-NWFET) to investigate its piezoresistive behavior. The channel diameter-dependent piezoresistive properties of the gate-all-around (GAA) JL-NWFET have been studied in detail. The GAA JL-NWFET with twin SiNWs channel of 20-nm diameter has been fabricated with the top–down approach, and the maximum gauge factor (GF)~80 has been observed. The simulation results have confirmed that the GF of the GAA JL-NWFET increases with decreasing the NW diameter. The GF of the 10-nm device has reached as high as ~200 in comparison with larger diameter GAA JL-NWFET. The simulation models have been validated by calculating the drain current and piezoresistive characteristics of the GAA JL-NWFET under strained conditions. The effect of strain on the transport properties of NW GAA JL-NWFET has also been studied. The results demonstrate that the carrier mobility of the lower diameter NW has enhanced to 364 (10-nm NW) from 323 cm2/Vs (20-nm NW). Furthermore, the carrier mobility of the channel has boosted with increasing the applied strain on the channel of GAA JL-NWFET and resulting in the increased GF.
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