DFT methodology for memory testing on lower technological node

Abstract

Today's SOC designs contains large numbers of memories. These memories occupy most of the portion of system-on-a-chip (SOCs) and any failure in memory will affect the SOC operation. Therefore, testing of these embedded memories is required and important step in SOC manufacturing that screens out damaged chips. Memory Built- In Self-Test (MBIST) is a Design for Testability (DFT) approach in which a segment of a circuit on a chip, board, or system is utilized to test the circuit itself. As we continue to move towards the lower technological node, the complexity of device increases, so there are number of difficulties arising which includes greater test cost, time, power consumption and possibilities of arising new defect at smaller node. Therefore, the overall yield of SOC depends on memory yield. This paper presents testing of these embedded memories, which is capable of achieving yield and reliability requirements such as detection of faults, generation of patterns as well as validation without affecting the functionality using LV (logic vision) Flow.