A DFT and test pattern generation methodology for an ARM powered/spl reg/ SoC design

Abstract

This article describes the design-for-testability (DFT) methodology for an ARM powered SoC (system-on-a-chip) design which is named by Garfield and used for hand-held computing. Various test methods, including scan insertion, memory BIST (built-in self-test), boundary scan and functional test, and the strategies merging the above methods in SoC design are discussed in detail.