DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits

Abstract

Event-driven asynchronous circuits are gaining attention because of their low power consumption and robustness. Among asynchronous circuits, the Bundled data (BD) circuit used by Loihi has attracted attention because it can obtain a similar area as a synchronous circuit. Click circuit is a mainstream BD circuit, but due to the lack of DFT (Design For Test) architecture, the Click-based asynchronous circuit cannot be widely used. This paper proposes a DFT architecture suitable for BD circuits, which can be accomplished using traditional EDA tools rather than developing new ones. This paper verifies the proposed DFT architecture on a five-stage pipeline processor based on the RISC-V instruction set. The result is 99.62% coverage for stuck-at faults, 1.8398% area overhead, and 6.2259% power overhead.