Abstract
We present design for balance testability (DFBT), a systematic signature-based method for enhancing the testability of logic circuits. DFBT employs balance testing and guarantees 100% coverage of single stuck-line faults, as well as many multiple stuck-line and bridging faults. The logic overhead of DFBT is modest|only one extra I/O pin and a small number of extra gates|and the original circuit need not be altered. We illustrate DFBT by applying it to representative logic circuits.
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