Device Verification Testing of High-Speed Analog-to-Digital Converters in Satellite Communication Systems

Abstract

This paper presents a step-by-step sequence of operations for the dynamic performance testing of a high-speed analog-to-digital converter (ADC) using on-chip digital demultiplexing and clock distribution. Demultiplexed digital outputs are postprocessed and fed into a computer-aided ADC performance characterization tool. The described methodology reduces test costs and overcomes many test hardware limitations. The problems of high-sampling-rate ADC testing are described. As our focus is on RF communication system applications, we emphasize the measurement of intermodulation distortion (IMD) and effective resolution bandwidth (ERB). Accurate gain and phase matching are also of critical importance. As Fourier analysis is an important component of characterization, we address the issue of automated sample window adjustment to eliminate leakage and false spur generation. A 6-bit 800 MSample/s dual-channel SiGe-based ADC is used as a target example.