Device scaling physics and channel velocities in AIGaN/GaN HFETs: velocities and effective gate length

Abstract

This paper addresses scaling issues in AIGaN/GaN heterojunction field-effect transistors (HFETs) using ensemble Monte Carlo techniques. For gate lengths below 0.25 /spl mu/m, f/sub T/ values are known not to scale linearly with the inverse gate length. The authors' simulations show this to be due to an increasing difference between the lithographic gate length and the effective gate length as the devices shrink. The results for AIGaN/GaN are compared with In/sub 0.52/Al/sub 0.48/-In/sub 0.53/Ga/sub 0.47/As-InP devices, and the authors found that the limiting role of velocity overshoot and depletion region spread causes the GaN HFETs to have a peak f/sub T/ of /spl sim/ 220 GHz compared to /spl sim/ 500 GHz for InGaAs devices.