Device interference in GaAs quantum wire transistors and its suppression by surface passivation using Si interface control layer

Abstract

In order to establish feasibility of high density integration of gate-controlled GaAs nanodevices, this article investigates device interference in GaAs-based quantum wire transistors (QWRTrs) by using a side-gating test structure and attempts to suppress the observed anomalously large side-gating with surface passivation using a silicon interface control layer (Si ICL). QWRTrs were formed on AlGaAs∕GaAs etched quantum wires (QWRs) and were controlled by nanometer sized Schottky wrap gates. A Schottky side gate was formed at a distance dsg from the QWR. When dsg was large, the QWRTr showed weak side gating which can be explained by the electrostatic side gating. However, when the side gates was placed close to the nanowire with dsg<500nm, anomalously large side gating started to take place which cannot be explained by the electrostatic side gating. On the basis of detailed measurements of side-gating behavior and side-gate leakage currents at various temperatures, the anomalous side gating was explained by a model in which occupation of deep traps at the back AlGaAs∕GaAs interface of the QWR is modulated by tunneling injection of electrons from the side-gate edge resulting from strong Fermi level pinning by surface states. Based on this model, attempts to reduce surface states by surface passivation were made. Formation of the Si ICL structure on a regrown thin GaAs cap layer completely removed the anomalous side-gating effect.