Device Design Considerations for Ion Implanted n-Channel MOSFETs

Abstract

Device design considerations are presented for ion implanted, n-channel, polysilicon gate, enhancement-mode MOSFETs for dynamic switching applications. A shallow channel implant is used to raise the magnitude of the gate threshold voltage while also maintaining a low substrate sensitivity (i.e., without substantially increasing the dependence of the threshold voltage on the source-to-substrate backgate bias). Design trade-offs between channel implantation energy and dose and substrate bias were examined using both computer analyses and experimental devices. The design objective was to identify the combination of these three parameter values that gives both a low substrate sensitivitya nd a steep subthreshold conduction characteristic under the conditions of a gate threshold voltage of 1 V and a substrate bias range of 0 to -1 V. One-dimensional and two-dimensional computer analyses were performed to predict the effect of the device parameters on the electrical characteristics. MOSFETs were then fabricated to investigate the extremes of the design parameter range, and the experimental and predicted device characteristics were compared. An enclosed device structure proved particularly useful in evaluating the subthreshold characteristic at very low values of drain current.