Device design assessment of 4H–SiC n-IGBT – A simulation study

Abstract

A theoretical design assessment is presented using two dimensional numerical computer aided design (TCAD) tool for 15–20kV 4H–SiC IGBTs. Physical parameters of the layer structures such as drift layer thickness, doping in the drift layer, JFET region width and interface charges underneath the gate region are varied to predict the device performance. Performance is further assessed at different temperatures and with different carrier lifetime in the drift layer. Using identical set of physical device parameters (doping, thicknesses), simulated structure was first calibrated with the experimental data. Simulations show that a minority carrier lifetime in the drift layer of 1.0–1.6μs produces a close match with the experimental device. An on-resistance first decays with temperature (i.e., increased in ionization level, and increase in minority carrier lifetime), stays nearly constant with further increase in the temperature (may be all carriers are now fully ionized and increase in carrier lifetime is compensated with decrease in the carrier mobility) and finally increases linearly with temperature (>450K) due to decrease in the carrier mobility. A significant increase in the forward voltage drop is observed with the presence of interface trap charges. Increasing JFET region width slightly decreases the forward on-state voltage. A drift layer of at least 175μm thick with a doping concentration of <2.0×1014cm−3 is required to get a blocking voltage of 20kV for 4H–SiC IGBTs assuming a minority carrier lifetime of 1μs in the drift layer.