Development of three-dimensional MOS structures from trench-capacitor DRAM cell to pillar-type transistor

Abstract

The author invented a trench-capacitor dynamic-random-access memory (DRAM) cell and applied the Japanese patent in 1975. The first trial development of trench-capacitor DRAM cell was presented in 1982 in 1-Mbit DRAM era. This might be the first attempt to utilize vertical wall of silicon substrate for metal-oxide-semiconductor (MOS) structure. Subsequent to this trial various kinds of vertical-channel MOS transistors have been proposed in integrated circuits field. This presentation will describe circumstances of invention and development of the trench-capacitor DRAM cell and subsequent development of several vertical-channel MOS transistors done by the author?s group.