Development of substrate-pumped nMOS protection for a 0.13 μm technology

Abstract

A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complemented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the substrate-pumped nMOS can provide dramatically higher protection than estimated from conventional I t2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a substrate-pumped protection circuit. A systematic approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.