Development of substrate engineered Si-/[100] Patterned Features by anisotropic wet etching with Pt/Pt3Si mask

Abstract

In the current article, a substrate engineered patterned array of square-shaped features of size 1.5 μm × 1.5 μm comprising of <111>/[100]-planes of p-Si substrate has been developed by employing electron beam lithography assisted selective anisotropic wet etching. The etching of such planes is performed by combining the effect of KOH as the chemical etchant and Pt/Pt3Si as the mask with its catalyzing properties for the etching reaction. The regular array of exposed <111>/[100]-planes is confirmed by FESEM imaging and X-ray diffraction study. The formation of a ‘virtual hetero-junction’ at <111>/[100] interface is characterized by in-situ current-voltage measurement within the FESEM chamber. Such surface engineered Si-substrates can be utilized for multifaceted applications by fabricating different types of electronic, optoelectronic and bio-sensing devices.