Development of sub-10-nm atomic layer deposition barriers for Cu/low- k interconnects

Abstract

The development of atomic layer deposition (ALD) barriers with a thickness below 10 nm for copper/low- k dielectric interconnects was reviewed. The CMOS 65-nm technology node, which is presumably the first node, at which ALD barriers will be employed, was taken as a reference. The ALD barrier process will most likely meet the geometrical requirements, i.e. the capability to deposit barrier films in narrow dimensions. In order to establish the compliance of ALD barriers with the thickness requirements, the growth of the ALD layer was investigated. It was shown that the growth of the ALD films proceeds via islands, which are formed in the nucleation step. The thickness, which is necessary to close the surface of the substrate, depends on process conditions and barrier material. It is argued that the minimum barrier thickness should be at least of the same order as the thickness to achieve closure. In the 65-nm technology node barriers have to be compatible with low- k dielectric materials. To achieve growth of ALD barriers on dense low- k materials, surface treatments of the dielectric films have to be implemented. The deposition of ALD films on dielectric materials with an interconnected pore structure results in penetration of the ALD precursors into the pore system and deposition of the barrier inside the dielectric material.