Abstract
Logic simulation is the process of exercising a realistic model of a digital system with sets of input stimuli. Computation time required for logic simulation is growing due to recent increases in the size, complexity and test requirements of the systems to be simulated. Hence, this has become one of the most important subjects in the area of computer-aided design. The objective of this research was to develop and implement a new speed-up algorithm which decreases computing requirements for software simulation. A reduced time interval partitioned simulation algorithm is presented. This new algorithm is based on a time first evaluation algorithm and the reduction of time intervals. The new algorithm partitions the circuit into standard subcircuits and searches the time intervals where the output value of a primitive is determined. It only evaluates the events which are not including in those time intervals. This new simulation algorithm is shown to be faster and more efficient than conventional algorithms.
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