Abstract
The single-phase phase-locked loop (PLL) is essential for the stable operation and control of single-phase grid-connected converters. However, in practical applications, the grid voltage is usually affected by harmonics and dc offset, which will cause errors in the output of the PLL. Therefore, using sliding discrete Fourier transform filter (SDFT) as a prefilter, this paper proposes an improved single-phase synchronous reference frame PLL with a fixed sampling frequency, which can accurately and quickly obtain the grid parameters under distorted grid conditions. Most importantly, the paper theoretically analyzes phase and amplitude errors generated by SDFT for the first time and a quantitative compensation method is proposed, which is straightforward to be used by a reader. Finally, the proposed PLL is compared with other PLLs through simulation and experiments. The experimental results show the effectiveness and practicability of the proposed method.
Highlights
In recent years, single-phase grid-connected power conditioning systems such as pulse width modulation (PWM) rectifier [1], active power filters, distributed generation, uninterruptible power supplies (UPS), etc. have attracted more and more attention [2]
The block diagram of the single-phase phase-locked loop (PLL) is shown in Fig. 1, which consists of three parts: 1) phase detector (PD), 2) loop filter (LF), 3) voltage controlled oscillator (VCO)
In the case of asynchronous sampling, this article theoretically analyzes the phase and amplitude errors generated by sliding discrete Fourier transform filter (SDFT) for the first time, and proposes a compensation algorithm that is easy for readers to follow
Summary
Single-phase grid-connected power conditioning systems such as pulse width modulation (PWM) rectifier [1], active power filters, distributed generation, uninterruptible power supplies (UPS), etc. have attracted more and more attention [2]. The above methods work well under ideal conditions but these PLLs will suffer a large phase error under grid voltage disturbances such as harmonics, dc offset. [13] proposes dq-frame delayed signal cancellation based PLL (dqDSC2-PLL) It has a low response speed and a large estimated phase error when the grid distortion is serious. This paper analyzes the phase and amplitude offset errors generated by SDFT during asynchronous sampling for the first time, and proposes a quantitative compensation algorithm based on this analysis to improve the performance of the PLL under frequency changes. 1. In the case of asynchronous sampling, this article theoretically analyzes the phase and amplitude errors generated by SDFT for the first time, and proposes a compensation algorithm that is easy for readers to follow. In [27], the stability of the system is improved by adding the stability factor r < 1 and r is chosen to be 0.99999 in this paper
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