Development of Embedded Redistribution Layer-Based Silicon Interposer for 3-D Integration

Abstract

Silicon interposers that are typically composed of redistribution layers (RDLs) and through-silicon vias have become a popular alternative approach to achieve 3-D integration. However, issues including the long metallization duration and the risk of unacceptable interfacial resistance or even disconnection are prohibiting their wider adoption. In this paper, by substituting RDLs with conductive polymer-filled trenches at the bonding interface, a silicon interposer architecture with faster fabrication speed and better interfacial connection was developed. Ag-based and carbon-based (C-based) conductive polymers with different viscosities were tested under varying vacuum suction conditions. It was found that the filling ratio would increase more efficiently with the driving pressure. Besides, measurements indicated the average resistance of channels filled with Ag-based conductive polymers was in the range of 40– $55~\Omega $ . Furthermore, their resistivity stability and bonding strength to Cu and Al had proven to be promising during the temperature increase.