Modeling, Fabrication, and Characterization of Low-Cost and High-Performance Polycrystalline Panel-Based Silicon Interposer With Through Vias and Redistribution Layers

Abstract

Interconnections between integrated circuits and print circuit boards are primarily achieved currently with organic packages at high I/O pitch. Organic packages, however, are limited by poor thermal and dimension stabilities for them to act as fine pitch interposers. To address these challenges, silicon interposers are being developed. Current silicon interposers, based on through-silicon via (TSV) techniques, suffer from high production cost, because of expensive CMOS-grade silicon, expensive TSV process and smaller wafer sizes. They also suffer from high electrical loss in spite of thin SiO 2 interfacial layers. This paper, for the first time, demonstrates a lower cost and higher performance silicon interposer. It is based on panel-based polycrystalline silicon with through-package vias (TPVs) and redistribution layers, and a simple and double-side process with thick polymer liner inside the TPV. Electrical modeling was carried out that shows the better electrical performance of polycrystalline silicon interposer compared with traditional single-crystalline silicon interposer. The polycrystalline silicon interposer test vehicles with up to four metal layers were demonstrated and characterized. The measurement results showed good electrical performance and matched well with the simulations.