Development of dynamic reconfiguration implementation of AES on FPGA platform

Abstract

Dynamic partial reconfiguration is the ability of modern FPGA's to dynamically change some selected area(s) of the FPGA while rest of the design is running. This feature allows to reuse the same hardware for different applications. In this paper we have chosen various Advanced Encryption Standard (AES) key sizes, viz. 128-bit, 192-bit and 256-bit as parameter for reconfiguration. A dynamic reconfigurable implementation for high speed and low area AES has been developed on Digilent's Zed board (XC7z020CLG484-1). The proposed work implements two pipelined versions of AES for reconfiguration, (i) High speed version using modular pipelining, (ii) Area efficient version using simpler pipeline. Maximum operational frequencies of 389.25, 389.25 & 386.2 MHz have been achieved using modular pipelined approach, while 204.3, 203.7 & 146.5 MHz is obtained for simple pipelined approach corresponding to 128, 192 and 256-bit AES respectively. The obtained throughput ranges from 49.8 Gbps to 98.8 Gbps for modular pipeline, and from 26.15 to 39.11 Gbps for simple pipeline structure.