Abstract

Advanced Encryption Standard (AES) has replaced its predecessor, Double Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and power consumption due to more operations that need to be done. Some companies that employ ultra-high security in their systems may look for a key size bigger than 256-bit AES. In this paper, 128 and 256-bit AES hardware, as well as two variants of an AES encryption algorithm for 512-bit and 1024-bit key size, are implemented and compared in terms of power consumption and area. The experiment is done in 45 nm CMOS technology at 1.1 V using a Synopys DC Compiler and Modelsim and total power consumption and area results are presented and graphically compared.

Full Text
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