Development of cost-effective wafer level process for 3D-integration with bump-less TSV interconnects

Abstract

The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with −65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.