Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

Abstract

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.