Abstract
In this paper, the electrical failure is analyzed in failure map of 28nm logic pattern wafer. As CD shrinks to 28nm and beyond, the contact metallization face poor gap fill of tungsten and low process win tolerance, is like erosion and within-wafer uniformity. The poor interconnection between metal copper via and contact tungsten via of failure include metal1 (M1) Cu bridge and metal1 open. The M1 bridge is induced by large erosion at high contact via density. Another M1 open is induced by W recess at iso via. A novel non-selective slurry buff process provide non-selective removal speciality and splendid uniformity to reduce erosion and recess, are less than 50A to meet 28nm technology node and beyond.
Published Version
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