Development of a low power Delay-Locked Loop in two 130 nm CMOS technologies

Abstract

The design and measurement results of two low power DLL prototypes for applications in particle physics readout systems are presented. The DLLs were fabricated in two different 130 nm CMOS technologies, called process A and process B, giving the opportunity to compare these two CMOS processes. Both circuits generate 64 uniform clock phases and operate at similar frequency range, from 20 MHz up to 60 MHz (10 MHz – 90 MHz in process B). The period jitter of both DLLs is in the range 2.5 ps – 12.1 ps (RMS) and depends on the selected output phase. The complete DLL functionality was experimentally verified, confirming a very low and frequency scalable power consumption of around 0.7 mW at typical 40 MHz input. The DLL prototype, designed in process A, occupies 680 μm × 210 μm, while the same circuit designed in process B occupies 430 μm × 190 μm.