Abstract
This paper describes the design of a high-speed low-power 1-bit full adder cell. The main design objectives for this adder circuit are low power consumption and higher speed at low supply voltage. Using pseudo-NMOS together with two inverters this adder cell has been designed in 0.18-/spl mu/ CMOS process. Considering transistor chaining, grouping, and signal sequencing in our proposed adder layout which all have noticeable impacts on the circuit performance, shows substantial power saving and speed improvement at no area penalty. Inverters act as drivers. Therefore, each stage will not suffer degradation in its deriving capabilities. This saves power, area, and time. This adder cell in 0.18-/spl mu/ CMOS process has an average delay time of 0.077 ns. It also exhibits low average power dissipation of 0.156/spl times/10/sup -3/ W at frequency equal to 4 GHz. The proposed full adder circuit has shown to provide superior performance.
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