Abstract
In this research, an optimized process scheme for through glass via (TGV)/through silicon via (TSV) fabrication is proposed to solve the difficulty of copper (Cu) filling in TGV/TSV. Kelvin structure, daisy chain, and comb structure are fabricated for evaluating electrical performance. Comparison between TGV and TSV shows that the power loss and overall process steps (cost) of TGV is lower than TSV for 3D interconnect. Moreover, daisy chain structure at chip-level is fabricated and investigated on its reliability including thermal cycling and humidity test. Finally, TGV/TSV without voids and V-shape pits formed at the filler are successfully fabricated and demonstrated at chip-level with 50-µm TGV/TSV and 200-µm thinned wafers.
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