Developing Test Environment for Embedded Cores-Based System-on-a-Chip (SOC)

Abstract

The subject paper proposes developing test environment and test methodologies for digital embedded cores-based system-on-a-chip (SOC). The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE P1500-compliant. The test access mechanism plays an important role in transporting the test patterns to the desired core and the core responses to the output pin of the SOC. The faults were injected using a fault simulator that generates tests for the core. The cores and test access mechanism were described using Verilog HDL. The test access mechanism (TAM) provides the connection between the test sources, cores, and test sinks, and is crucial in any SOC design. There are many ways to design a TAM. In this paper, TAM was implemented as a plain signal transport medium, which is shared by all the cores in the system-on-a-chip. Once the compilation of the cores was successful, the fault simulation was carried out. The selection of the individual cores was taken care of by the program running in the background. The outcome was the fault coverage of all the cores being tested