Abstract

Capacitance–voltage ( C– V) technique is used to investigate the electronic properties of Si 0.3Ge 0.7 hetero layers deposited on fully relaxed-Si 0.4Ge 0.6. This is a fast and nondestructive method to determine important electronic properties, such as, apparent doping concentration, SiGe layer thicknesses, and threshold voltage and valence band offset in a heterostructure. Capacitance transient ( C– t) method has been used to determine minority carrier lifetime from the slope of the Zerbst plot and is found to be 23.9 μs. Interface properties of high-k gate dielectric (ZrO 2) deposited on SiGe has also been studied prior to transient capacitance measurements. Average midgap value of interface state density ( D it) extracted from high-frequency C– V measurement is found to be 1.1 × 10 12 cm − 2 eV − 1 .

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call