Abstract

The capacity/conductivity-voltage (C/G-V) data of the PVP interlayered metal-semiconductor structure were examined at ±4V biases and 1-500 kHz frequency interval at room temperature. The surface states ( $N_{ss}$ ) in the insulation layer and the metal-semiconductor interface are seen as the main causes of high capacitance and conductivity values at low frequencies. AC signals, which result in an increase in capacitance and conductivity values, are easily monitored by $N_{ss}$ at low frequencies. The graph extracted against the conductivity and frequency logarithm ( $G_{p}$ /ω-log(f)) indicates a peak appearance as a result of the $N_{ss}$ effect. In the energy range of ( $E_{c}$ −0.423) − ( $E_{c}$ −0.604), surface states ( $N_{ss}$ ) and relaxation times (τ) values alter from 8.71 × 1011 to 5.84 × 1011 eV−1 cm−2 and 6.54 × 10−6 s to 1.10 × 10−4 s, respectively.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.