Detection System of Single Event Upset Based on FPGA

Abstract

As the semiconductor process progresses into deep submicron nodes, single event upsets (SEUs) have severely deteriorated the reliability of Integrated circuits (ICs), especially for the satellite electronic equipment. Traditional methods of SEU is radiation scanning with fine resolutions over the surface for inspection, which is just sample test with workload statistics and experiences as the qualitative criterion, thus results in costly, time-consuming and error-prone test procedures. In this paper, we propose a SEU detection system based on FPGA by using the controllability and observability of scan chain, which can automatically generate test vectors for scan chain of DUT (design under test), analyze test results and synchronize irradiation source and DUT. Our proposed detection system not only reduce the cost of testing, but also increase the flexibility of testing. The proposed system can automatically detect the reliability of DUT and count the number of soft errors caused by SEU with low cost overhead. Experimental results on ISCAS’89 benchmark circuits implementation demonstrate the validity of this method.