Detection of multiple transitions in delay fault test of SPARC64 microprocessor

Abstract

This work presents a new non-robust delay fault test generation method for the purpose of screening delay defects of microprocessors with fewer test vectors. It is important to reduce the number of test vectors in order to reduce test time, memory usage in the tester, and the overall testing cost. By paying attention to the constraints of off-path inputs in a non-robust test, we made it possible to generate a pair of test vectors to detect multiple delay faults based on the traditional dynamic compaction technique. Delay fault test based on our method is applied to SPARC64 microprocessor with 1.3 GHz clock for screening delay defects, and we achieved 90% coverage with 3,567 test vectors. The comparison results also show that the robust test is not practical for the screening purpose, since it needs more than three times the number of test vectors as compared to the non-robust test.